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An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAMs

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5 Author(s)
Y. Tsukikawa ; LSI Lab., Mitsubishi Electr. Corp., Itami, Japan ; T. Kajimoto ; Y. Okasaka ; H. Miyamoto
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The authors propose an efficient back-bias voltage (Vbb) generator with a newly introduced hybrid pumping circuit (HPC). This hybrid system uses one NMOS pumping transistor and one PMOS pumping transistor and can pump as low as the -Vcc level without a Vth loss. By adopting a triple-well structure at the pumping circuit area, the NMOS transistor can be employed as a pumping transistor without minority carrier injection.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993