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Timing recovery circuits in magnetic recording systems have to have high bit rate and fast acquisition cycles, so they are usually equipped with an analog phase-locked loop (PLL). We propose a new method of digital timing recovery circuit that is different from the conventional digital PLL and that can be operated under a faster acquisition and wider capture range. This report describes the new digital timing recovery circuit architecture for magnetic recording that uses feedback delay compensators for fast acquisition and wide capture range on CMOS LSI circuit.
Date of Conference: 19-21 May 1993