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PLLs (phase locked loops) are expected to be desirable components for clock extraction in high speed digital communication systems, typically in optical systems, because of the low cost, compactness, suitability to integration, and ease of treatment. The PLL for clock extraction requires a fast pull-in and small output jitter characteristics. In this paper, we describe a total PLL system, in which a further improvement of the pull-in time is realized and a pseudo lock (i.e. harmonic lock), which has been a serious problem in the past, can be avoided automatically. We have constructed the PLL system using a monolithic PU-IC for the PLL core part and 1.2 micron design rule PLAs for most of the remaining part of the system, and measured total performances of the system.
Date of Conference: 19-21 May 1993