Referenced Items are not available for this document.
The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance. This scheme permits battery backup even for giga-scale LSIs.
Published in:
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Date of Conference: 19-21 May 1993
- Page(s):
- 47 - 48
- INSPEC Accession Number:
- 4764468
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.1993.920533
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
