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The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance. This scheme permits battery backup even for giga-scale LSIs.
Date of Conference: 19-21 May 1993