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A JPEG compliant Huffman decoder circuit has been developed. The circuit executes at 27 MHz in order to maintain image data transfer at CCIR 601 video rates. The circuit detects and decodes variable length Huffman codes in a single clock cycle by searching among all Huffman codes in the current table. The circuit utilizes a CAM with mask bits to perform this rapid search. The architecture also utilizes a double barrel shifter to window the next portion of the input bit stream to be examined, which makes the critical path as short as possible. According to the simulation results, the delay of execution in a cycle is 18.1 ns. The total memory size is 15K bits.