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Communication delay in circuit-switched interconnection networks

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3 Author(s)
Geyong Min ; Dept. of Comput. Sci., Glasgow Univ., UK ; M. Ould-Khaoua ; H. Sarbazi-Azad

Interconnection network design plays a central role in the design of parallel systems. The paper presents an analytical model to predict communication delay in circuit-switched k-ary n-cube interconnection networks augmented with virtual channel support. The main feature of the proposed model is the use of Markov chains to compute the path set-up time and to capture the effects of using virtual channels to reduce message blocking in the network. The mean waiting time that a message experiences at a source node before entering the network is calculated using an M/G/1 queueing system. The model is validated through flit-level simulation experiments

Published in:

Performance, Computing, and Communications, 2001. IEEE International Conference on.

Date of Conference:

Apr 2001