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Synthesizing a long latency unit within VLIW processor

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4 Author(s)
R. L. Gupta ; Alliance Semicond., Bangalore, India ; A. Kumar ; A. Van Der Werf ; G. N. Busa

With increasing high performance requirements, VLIW processors are becoming more and more popular. To go beyond the performance achievable by the use of a VLIW architecture, specialized functional units can be added to the processor. However, no single tool provides the capability of synthesizing such a processor. This paper shows a method to embed a long latency unit within a VLIW processor datapath using some available tools. Phideo, an architectural synthesis tool is used to synthesize a special high throughput unit. The high level synthesis tool, Mistral2, is used to generate the VLIW processor datapath and to compile microcode for it. The Phideo synthesized unit is interfaced as a functional unit in the Mistral2 datapath and Mistral2 scheduling is made compatible with the Phideo schedule. The motion estimation algorithm for MPEG-2 standard has been chosen as a case study to prove the methodology

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VLSI Design, 2001. Fourteenth International Conference on

Date of Conference: