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Complexity of minimum-delay gate

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2 Author(s)
S. Chakraborty ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India ; R. Murgai

Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gate-level circuits. In this paper, we study the complexity of two different minimum-delay gate resizing problems for combinational circuits composed of single output gates. The first problem is that of gate resizing for minimum circuit delay under the load-dependent delay model. The second problem is a variant of the first, where we relax the delay model to a load independent one, but impose load constraints instead, i.e., each gate output is not allowed to drive a capacitive load that exceeds its drive capacity. The goal, as before, is to minimize the delay through the circuit. To the best of our knowledge, there has been no published result on the complexity of these problems. In this paper, we prove that both problems are NP-complete. The proofs are inspired by Murgai's work [1999], in which the global fanout optimization problem under a fixed net topology was shown to be NP-complete. These results, along with previously published ones, establish that gate resizing is a hard problem except under the most simplistic assumptions

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VLSI Design, 2001. Fourteenth International Conference on

Date of Conference: