By Topic

Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Duarte, D. ; Pennsylvania State Univ., University Park, PA, USA ; Narayanan, V. ; Irwin, M.J. ; Kandemir, M.

Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001