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Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language

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4 Author(s)
Mishra, P. ; Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA ; Grun, P. ; Dutt, N. ; Nicolau, A.

Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations for programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. However, such a processor-memory co-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, and perform exploration of the memory architecture to trade-off cost versus performance. We present a set of experiments using our Memory-Aware Architectural Description Language to drive the exploration of the memory subsystem for the TIC6211 processor architecture, demonstrating a range of cost and performance attributes

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001