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Defect localization using physical design and electrical test information

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5 Author(s)
Z. Stanojevic ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; H. Balachandran ; D. M. H. Walker ; F. Lakhani
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In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injected via FIB. Preliminary failure analysis results on production defects are promising

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Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

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