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Technology assessment of commercially available critical area extraction tools

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3 Author(s)
C. Long ; SEMATECH, Austin, TX, USA ; D. Maynard ; M. A. Bjornsen

In the 1990s, the semiconductor industry witnessed a philosophical change in the subject of modeling wafer final test yields. The calculation of average faults per chip has been historically calculated as the product of chip area and fault density, and often incorrectly referred to as defect density. For more than 20 years, several pioneering researchers, representing both academia and industry, have advocated a more accurate estimation of average faults per chip by using critical area, a better metric of chip sensitivity to defect mechanisms. The implementation of this concept requires sophisticated software tools that interrogate the physical design data. At the request of the member companies, International SEMATECH launched a study in 1999 of four commercially available critical area extraction (CAE) tools, with a primary objective of providing an independent technical assessment of capability, performance, accuracy, ease of use, features, and other distinguishing characteristics. Each of the tools were run on several product designs from Agilent Technologies and IBM Microelectronics. The CAE tools were all installed and evaluated at a common member company location, and each of the tool suppliers were visited, providing detailed visibility into the supplier's environment. This paper will review the evaluation methodology, and summarize the findings and results of this International SEMATECH sponsored study

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Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

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