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Solder bump reliability-issues on bump layout

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3 Author(s)
Alander, T. ; Inst. of Electron., Tampere Univ. of Technol., Finland ; Heino, P. ; Ristolainen, E.

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder. Simulations are performed with varying bump placement, underfill coverage and board size. The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package. Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size and the inclusion of heat transfer bumps.

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:23 ,  Issue: 4 )