Referenced Items are not available for this document.
A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 μm CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB.
Published in:
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Date of Conference: 2000
- Page(s):
- 225 - 227
- Print ISBN:
- 1-58113-190-9
- INSPEC Accession Number:
- 6804829
- Digital Object Identifier :
- 10.1109/LPE.2000.155285
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
