Referenced Items are not available for this document.
New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach
Published in:
Design & Test of Computers, IEEE
(Volume:17
,
Issue:
3
)
Date of Publication: Jul/Sep 2000
- Page(s):
- 44 - 53
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 6699342
- Digital Object Identifier :
- 10.1109/54.867894
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jul/Sep 2000
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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