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RT-level ITC'99 benchmarks and first ATPG results

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3 Author(s)
Corno, F. ; Politecnico di Torino, Italy ; Reorda, M.S. ; Squillero, G.

New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach

Published in:

Design & Test of Computers, IEEE  (Volume:17 ,  Issue: 3 )

Date of Publication:

Jul/Sep 2000

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