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A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 m of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.