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1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus

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7 Author(s)
Zerbe, J.L. ; Rambus Inc., Mountain View, CA, USA ; Chau, P.S. ; Werner, C.W. ; Thrush, T.P.
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A 1.6 Gb/s/pin 4-PAM multi-drop signaling system has been implemented in 0.35-/spl mu/m CMOS. The system uses current-mode single-ended signaling, with three DC references shared across six I/O pins. A high-gain windowed integrating receiver with wide common-mode range was designed in order to improve SNR when operating with the smaller input overdrive of 4-PAM. Voltage and timing margins are measured via shmoos in a two-drop bussed system.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000

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