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A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs

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5 Author(s)
T. Hamamoto ; ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan ; S. Kawasaki ; K. Furutani ; K. Yasuda
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This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000