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A 5.2-GHz CMOS receiver with 62-dB image rejection

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1 Author(s)
Razavi, B. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-/spl mu/m digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP/sub 3/ of -15 dBm, and a voltage conversion gain of 43 dB while draining 24 mW from a 2.5-V supply.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000