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Latched CMOS differential logic (LCDL) for complex high-speed VLSI

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2 Author(s)
Chung-Yu Wu, Ph.D. ; Nat. Chiao Tung Univ., Hsin-Chu, Taiwan ; Kuo-Hsing Cheng

A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 9 )