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Yield optimization in large RAM's with hierarchical redundancy

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3 Author(s)
K. N. Ganapathy ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; A. D. Singh ; D. K. Pradhan

The authors present and analyze large RAM architectures with hierarchical redundancy and determine the optimal redundancy organization for yield enhancement. A two-level redundancy scheme is used for defect tolerance, and the defect distribution is modeled using the compounded Poisson model. The tree random access memory (TRAM), which has been proposed as a design methodology for future multimegabit memories (N. Jarwala et al., 1988) is considered as an example for modeling and optimization. The results show that the two-level hierarchical redundancy approach, with spare bit and word lines within memory quadrants, and additional spare modules for global sparing, along with redundant interconnections can efficiently provide defect tolerance and viable yields for future generations of high-density dynamic random access memories

Published in:

IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 9 )