Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels

A new high-speed and low-power threshold detector is proposed to realize high-performance arithmetic VLSI systems. In a conventional threshold detector with a single supply voltage, the input signal swing of a differential-pair circuit (DPC) is too large, which causes large power dissipation together with a long switching delay. The use of two kinds of supply voltages makes the input signal swing of the DPC small, which results in a lower power dissipation together with a higher switching speed. As a typical example of the proposed multiple-valued current-mode (MVCM) logic circuit, a radix-2 signed-digit full adder is designed by using a 0.35 μm CMOS technology. Its performance is superior to that of a corresponding MVCM logic circuit with a single supply voltage under the same transistor counts