By Topic

High-radix parallel VLSI dividers without using quotient digit selection tables

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Aoki, T. ; Dept. of Syst. Inf. Sci., Tohoku Univ., Sendai, Japan ; Nakazawa, K. ; Higuchi, T.

This paper presents the design and evaluation of high-radix parallel dividers for high-speed signal and data processing applications. The presented divider designs are based on the unified high-radix division algorithm proposed by the authors. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with less hardware complexity, in comparison with the binary counterparts. This paper also presents the experimental fabrication of the radix-4 divider in 0.35 μm CMOS technology

Published in:

Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

Date of Conference: