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Wafer-level chip scale packaging: benefits for integrated passive devices

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4 Author(s)
Clearfield, H.M. ; Intarsia Corp., Fremont, CA, USA ; Young, J.L. ; Wijeyesekera, S.D. ; Logan, E.A.

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:23 ,  Issue: 2 )