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Wafer-level chip size package (WL-CSP)

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9 Author(s)
M. Topper ; Fraunhofer Inst. of Reliability & Microintegration, Berlin, Germany ; S. Fehlberg ; K. Scherpinski ; C. Karduck
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Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost

Published in:

IEEE Transactions on Advanced Packaging  (Volume:23 ,  Issue: 2 )