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Hardware resource minimization for histogram-based ADC BIST

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4 Author(s)
Renovell, M. ; Lab. d''Inf. Robotique Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France ; Azais, F. ; Bernard, S. ; Bertrand, Y.

The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimuli and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical hardware-consuming concurrent calculations by hardware-saving time-spread calculations. The decomposition technique is used both at high level (specific test phases are dedicated to each ADC parameter computation) and low level (sequential steps inside each test phase). Pseudo-algorithms are given to derive offset, gain error and nonlinearities

Published in:

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference:

2000

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