Close category search window
 

Design of 25-nm SALVO PMOS devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Vuong, H.H. ; Bell Labs., Lucent Technol., Murray Hill, NJ, USA ; Chang, C.P. ; Pai, C.S.

The concept and preliminary designs of novel self-aligned local-channel V-gate by optical lithography (SALVO) devices are presented. SALVO uses optimized local-channel doping to sharpen the lateral junctions, in order to minimize short channel effects for gate lengths down to 25 nm. In addition, it utilizes the replacement-gate design with inner spacers to facilitate integration of alternative gate stack materials and to extend the application of optical lithography. SALVO PMOS designs with both metal gate and poly-metal gate electrodes were studied, the latter proving capable of delivering high performance 25 nm PMOS with currently manufacturable processes.

Published in:
Electron Device Letters, IEEE  (Volume:21 ,  Issue: 5 )

Date of Publication: May 2000

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.