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Implementation of a 3rd-generation SPARC V9 64 b microprocessor

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29 Author(s)
Heald, R. ; Sun Microsyst., Palo Alto, CA, USA ; Aingaran, K. ; Amir, C. ; Ang, M.
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This 3rd-generation, superscalar processor, implementing the SPARC V9 64 b architecture, improves performance over previous processors by improvements in the on-chip memory system and circuit designs enhancing the speed of critical paths beyond the process entitlement. In the on-chip memory system, both bandwidth and latency are scaled. Keys to scaling memory latency are a sum-addressed memory data cache, which allows the average memory latency to scale by more than the clock ratio, and the use of a prefetch data cache. Memory bandwidth is improved by using wave-pipelined SRAM designs for on-chip caches and a write cache for store traffic. The chip operates at 800 MHz and dissipates <60 W from a 1.5 V supply. It contains 23 M transistors (12 M in RAM cells) on a 244mm/sup 2/ die. This paper contrasts this 7-metal-layer-aluminum, 0.15 /spl mu/m CMOS design with the previous generations designs. To deal with the growing microprocessor complexity, more aggressive circuit-techniques, interconnect delay optimization, crosstalk reduction, improved power and clock distribution schemes, and better thermal management are used.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000