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Improved RF capability and projected increase in die size for CMOS circuits lead to the concept of wireless communications within and between chips. A potential application is wireless clock distribution, proposed as an alternative interconnect system capable of distributing high frequency clock signals at the speed of light using microwaves. The wireless clock distribution system consists of a clock transmitter, located on or off chip, broadcasting a microwave global clock signal at frequencies greater than 15 GHz, and a grid of integrated clock receivers. The global clock signal is received using an integrated dipole antenna. The signal is then amplified using a low-noise amplifier (LNA), frequency divided down to the local clock frequency, buffered, and distributed to provide local clock signals. This IC operating at 7.4 GHz, which integrates antennas and necessary receiver circuits in 0.25 /spl mu/m CMOS with five metal layers on p-substrates, is a first step towards realizing such a system.