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The increasing need for interconnect bandwidth between ICs on PCBs together with limited pin count demands high-speed serial interfaces. Many fast serial transceivers have been published in this field, but they are rather large, noisy and/or power hungry for embedded applications, especially in a mixed-signal environment. For short-distance communication, phase-locked clock recovery and oversampling, are quite 'expensive' techniques for data recovery and synchronization, resulting in fixed wordlengths protocols and limited flexibility. Interchip interconnect research focuses on driver techniques and throughput per pin. Serial transfer of parallel data and synchronization issues are not discussed. The solution presented in this paper is simple, robust and flexible and has low electromagnetic interference (EMI). This makes it especially suitable for data busses between AD/DA converters and a microprocessor or DSP, although it can be applied for other bus types as well. While a prototype is implemented in standard 0.35 /spl mu/m CMOS, the concept can be used in many technologies and is future-proof, regarding signaling levels and circuit techniques.