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VLSI system design using asynchronous wave pipelines: a 0.35 μm CMOS 1.5 GHz elliptic curve public key cryptosystem chip

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3 Author(s)
O. Hauck ; Dept. of Comput. Sci. & Electr. Eng., Tech. Univ. Darmstadt, Germany ; A. Katoch ; S. A. Huss

This paper presents VLSI system design using asynchronous wave pipelines (AWPs) with a public key crypto chip as an example. The design challenges imposed by the crypto chip include very wide data paths, bit-level wave pipelining, hierarchical control resulting in different frequency domains, and interfacing synchronous registers with asynchronous controllers and data paths. The timing analysis indicates that AWPs operate more safely than synchronous wave pipelines. At the circuit level, SRCMOS is shown to be superior to previously proposed logic styles for wave pipelining. The same circuit style applies for both data path and control. Following some mathematics and cryptography background, the architecture of the chip is detailed whose outstanding feature is a wave pipelined Massey-Omura finite field multiplier. Simulations from layout of key circuits running at a rate of 1.5 GHz in a 0.35 μm CMOS process demonstrate the feasibility of the AWP concept

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Advanced Research in Asynchronous Circuits and Systems, 2000. (ASYNC 2000) Proceedings. Sixth International Symposium on

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