By Topic

On the design of fast, easily testable ALU's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
R. D. Blanton ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; J. P. Hayes

A design methodology for implementing fast, easily testable arithmetic-logic units (ALUs) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either /spl theta/(N) complexity (Lin-testable) or /spl theta/(1) complexity (C-testable), where N is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lintestable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lintestable ALU is only 0.5%.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:8 ,  Issue: 2 )