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Modeling of interconnect capacitance, delay, and crosstalk in VLSI

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3 Author(s)
Shyh-Chyi Wong ; Technol. Dev. Center, Winbond Electron. Corp., Hsinchu, China ; Gwo-Yann Lee ; Dye-Jyun Ma

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:13 ,  Issue: 1 )