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Fault-tolerant serial-parallel multiplier

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2 Author(s)
Chen, L.G. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chen, T.-H.

The paper presents a fault-tolerant circuit design using a time-redundancy method for a serial-parallel multiplier, which is useful in DSP applications with serial data transmission. It utilises the (RECO recomputing with circularly shifted operands) technique to detect errors concurrently. A simple OR-gate based circuit is used as the location table to identify faulty bit-slice pairs. The reconfiguration technique is then introduced to bypass the potential faulty bit-slices. This design can have the maximum detectable error region ( equivalent to n/2 bits), without appending extra computing elements. The latency from error detection to location is only about two clock cycles, i.e. almost real-time detecting can be achieved. Pipe-lined timing for two computations is illustrated. The analyses of performance and complexity are described. The results that this is an efficient design methodology for fault-tolerant multiplication with serial data.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:138 ,  Issue: 4 )

Date of Publication:

Jul 1991

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