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A high-speed CMOS track/hold circuit

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11 Author(s)
Mohamed Zin, M.A. ; Dept. of Electron. Eng., Gunma Univ., Japan ; Kobayashi, H. ; Kobayashi, K. ; Ichimura, J.-I.
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This paper describes the design of a high-speed CMOS track/hold circuit in front of an ADC. The track/hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 μm CMOS BSIM 3v3 parameters showed that it achieves the signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption. A test circuit was fabricated with MOSIS 0.8 μm CMOS process and its measured results show that the proposed circuit topology performs a track/hold operation

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Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on  (Volume:3 )

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