By Topic

Inductive noise reduction at the architectural level

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Pant, M.D. ; Georgia Inst. of Technol., Atlanta, GA, USA ; Pant, P. ; Wills, D.S. ; Tiwari, V.

A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach gigascale integration, chip power consumption is becoming a critical system parameter Deactivating idle units provides needed reductions in power consumption. However it introduces inductive noise that can limit voltage scaling. The paper introduces an architectural approach for reducing this inductive noise by providing gradual activation and deactivation of functional blocks. This technique provides a 2× reduction in ground bounce current on a 16 bit ALU simulated in SPICE, while reducing simulated SPEC95 performance by less than 5% on a typical superscalar architecture. It has also been demonstrated to be effective for image processing SIMD architectures

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: