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High-speed CORDIC architecture based on redundant sum formation and overlapped σ-selection

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3 Author(s)
Jae Hun Choi ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Jae-Hyuck Kwak ; Swartzlander, E.E.

This paper presents an architecture for accelerating CORDIC vectoring mode operations. The processing is sped up by overlapping redundant sum formation and selection of rotation direction. We analyze the latency time and area, and compare them with a conventional CORDIC implementation. The results show that the proposed scheme reduces not only the the latency but also the overall computation time. Thus, it achieves higher throughput in pipelining

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference:

1999

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