Referenced Items are not available for this document.
This paper describes a 0.25-μm, 64 K×36 bit pipelined burst SRAM using a 6.156-μm2 cell. It realizes over 500-MHz operation using a lower cost double metal process, Internal 16 K×144 organization by T-shaped bit line array reduces 20% of latency, 20% of active power, and 8.5% of die size. The low power also enables us to use lower cost thin quad flat type packages. Our solution to the soft error problem, a shallow triple well structure and four-transistor cell with stacked capacitor, improved soft error rate by 3.5 orders of magnitude compared with the conventional SRAM cell
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:34
,
Issue:
11
)
Date of Publication: Nov 1999
- Page(s):
- 1571 - 1579
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 6418535
- Digital Object Identifier :
- 10.1109/4.799865
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1999
- Sponsored by :
- IEEE Solid-State Circuits Society
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