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An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

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9 Author(s)
Cangsang Zhao ; Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA ; U. Bhattacharya ; M. Denham ; J. Kolonsek
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An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data transfer rate with 1.54-Gbit/s/pin I/O's. The SRAM is fabricated on a 0.18-μm CMOS technology. The 14.3×14.6-mm2 SRAM chip uses a 5.59-μm2, six-transistor cell. Circuit techniques used for achieving high bandwidth include fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-speed data-capture technique, a reduced-swing output buffer, and a high-sensitivity, high-bandwidth input buffer

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 11 )