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A seventh-generation x86 microprocessor

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14 Author(s)
Golden, M. ; Adv. Micro Devices Inc., Sunnyvale, CA, USA ; Hesley, S. ; Scherer, A. ; Crowley, M.
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An out-of-order, three-way superscalar ×86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three ×86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 11 )

Date of Publication:

Nov 1999

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