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Future perspective and scaling down roadmap for RF CMOS

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9 Author(s)
E. Morifuji ; Microelectron Eng. Lab., Toshiba Corp., Yokohama, Japan ; H. S. Momose ; T. Ohguro ; T. Yoshitomi
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Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999