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A fully integrated 5 GHz phase locked loop- (PLL-) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. A voltage-controlled differential injection-locked frequency divider (VCDILFD) is used as the first frequency divider in the PLL feedback loop to reduce power consumption and eliminate the need for an off-chip frequency divider. The total synthesizer power consumption is 32 mW. The phase noise is measured to be -101 dBc/Hz at 1 MHz offset frequency. The PLL bandwidth is 300 kHz and the measured spurious level at the adjacent channel is less than -54 dBc.