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Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.