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An 8 b 100 MSample/s CMOS pipelined folding ADC

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3 Author(s)
Myung-Jun Choe ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Bang-Sup Song ; Bacrania, K.

When applied to folding ADCs, pipelining relieves the wide bandwidth requirement of the folding amplifier. A pipelined folding ADC prototyped using a 0.5 /spl mu/m CMOS process exhibits a DNL of /spl plusmn/0.4 LSB and an INL of /spl plusmn/1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm/spl times/1.2 mm in active area and consumes 165 mW at 5 V.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999