Referenced Items are not available for this document.
This paper describes a low power, 1 Gbps, CMOS link with measured bit error rate (BER)<10/sup -14/. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750 MHz generates four phase sampling clocks.
Published in:
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Date of Conference: 17-19 June 1999
- Page(s):
- 47 - 48
- Meeting Date :
- 17 Jun 1999-19 Jun 1999
- Print ISBN:
- 4-930813-95-6
- INSPEC Accession Number:
- 6505332
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.1999.797231
- Product Type:
- Conference Publications
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