By Topic

An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Ah-Lyan Yee ; Texas Instrum. Inc., Dallas, TX, USA ; Gu, R. ; Heng-Chih-Lin ; Tsong, A.
more authors

This paper describes a high speed, low jitter CMOS transceiver, which includes 10 to 1 full duplex serialize-deserialize function, clock recovery, high speed differential I/O, and Built In Self Test (BIST). It was fabricated and tested to work at wide frequency range (1 to 2.5 Gbps) with low jitter and low power (76 ps P-P, 500 mW @ 2.5 Gbps). It was designed to be a component of ASIC standard cell library and was implemented as a stand alone design as well as in a large design with 32 transceivers.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999