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A 144 Mb 8-level NAND flash memory with optimized pulse width programming

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13 Author(s)
H. Nobukata ; Div. of Memory, Sony Corp., Kanagawa, Japan ; S. Takagi ; K. Hiraga ; T. Ohgishi
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Recently, the demand for high density flash memory for mass storage applications has grown. The most effective approach to improve memory density is a multi-level cell, however, the precise Vth control, which is indispensable to the multi-level cell, leads to the decrease of programming throughput. We have developed a 144 Mb 8-level NAND flash memory with 0.5 MB/s programming throughput which is 1.7 times faster than the conventional simultaneous programming scheme used in NAND flash memory. This high throughput has been attained by optimized pulse width programming. This chip employs the compact latch layout, which four adjacent 3-bit latches share one unit of the read/verify control circuit.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999