A formulation for quick evaluation and optimization of digital CMOS circuits

Most CMOS inverter models in the literature express the delay in terms of a load capacitance from which the effect of changing the sizes of the transistors is not immediately clear. In this paper, we introduce a first-order formulation based on the widths of the transistors for quick evaluation and optimization of the delay and energy in digital CMOS circuits. We then apply the formulation to obtain simple, closed-form expressions for a number of important parameters. These parameters include the optimum transistor sizing for minimizing the propagation delay, rising delay, falling delay, and energy-delay product. Furthermore, we demonstrate the convenience of using the model by applying it to a number of circuit scenarios.