Specification and verification of VLSI systems

A hardware verification approach based on linear time temporal logic is described. The authors show that by introducing appropriate abbreviations into linear temporal logic, which facilitate the expression of precise timing constraints, they obtain a very convenient language for the description of the behavior of hardware systems, and for the development of a formal verification system used in proving that designs meet their specifications. The authors automatically verified several sequential circuits. As an example they describe the specification and verification of an edge-triggered D-type flip-flop and the discovery of an error in a published specification. It is demonstrated that the approach is practical and offers a viable alternative to simulation. Comparison is made with other formal methods.<>