Referenced Items are not available for this document.
In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently
Published in:
Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on
Date of Conference: 1999
- Page(s):
- 108 - 121
- Meeting Date :
- 19 Apr 1999-21 Apr 1999
- ISSN :
- 1522-8681
- Print ISBN:
- 0-7695-0031-5
- INSPEC Accession Number:
- 6415612
- Conference Location :
- Barcelona
- Digital Object Identifier :
- 10.1109/ASYNC.1999.761527
- Product Type:
- Conference Publications
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